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? semiconductor components industries, llc, 2007 february, 2007 ? rev. p0 1 publication order number: ncp1396/d NCP1396A, ncp1396b product preview high performance resonant mode controller featuring high?voltage drivers the ncp1396 a/b of fers everything needed to build a reliable and rugged resonant mode power supply. its unique architecture includes a 500 khz voltage controller oscillator whose control mode brings flexibility when an oring function is a necessity, e.g. in multiple feedback paths implementations. thanks to its proprietary high ? voltage technology, the controller welcomes a bootstrapped mosfet driver for half ? bridge applications accepting bulk voltages up to 600 v. protections featuring various reaction times, e.g. immediate shutdown or timer ? based event, brown ? out, broken opto ? coupler detection etc., contribute to a safer converter design, without engendering additional circuitry complexity. an adjustable deadtime also helps lowering the shoot ? through current contribution as the switching frequency increases. features ? high ? frequency operation from 50 khz up to 500 khz ? 600 v high ? voltage floating driver ? selectable minimum switching frequency with 3% accuracy ? adjustable deadtime from 100 ns to 2 s. ? startup sequence via an adjustable soft ? start ? brown ? out protection for a simpler pfc association ? latched input for severe fault conditions, e.g. over temperature or ovp ? timer ? based input with auto ? recovery operation for delayed event reaction ? enable input for immediate event reaction or simple on/off control ? v cc operation up to 20 v ? low startup current of 300 a ? 1 a / 0.5 a peak current sink / source drive capability ? common collector optocoupler connection for easier oring ? internal temperature shutdown ? b version features 10 v v cc startup threshold ? so16 or dip16 package typical applications ? flat panel display power converters ? high power ac/dc adapters for notebooks ? industrial and medical power sources ? offline battery chargers pdip ? 16 p suffix case 648 pin connections http://onsemi.com marking diagrams x = a or b a = assembly location wl = wafer lot yy, y = year ww = work week g = pb ? free package so ? 16 d suffix case 751b 1396xdr2g awlyww 1 16 1 2 3 4 5 6 7 8 16 15 14 12 11 10 9 (top view ) bo css fmax ctimer rt fb dt fast fault vboot mupper vcc mlower slow fault hb gnd 13 nc see detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet. ordering information *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 16 1 16 1 ncp1396xp awlyywwg
NCP1396A, ncp1396b http://onsemi.com 2 figure 1. typical application example c9 r19 c8 r9 c10 r7 r14 r18 r13 vout l1 r23 d4 c6 + m1 m2 r10 r11 t1 d1 d2 + c13 c1 r16 d7 d9 c14 r21 slow input c12 c7 + d3 c11 r6 soft ? start fmax dt bo skip selection rt ovp fb u2a fast input u5 d8 r20 r24 r8 r17 u3a timer hv r2 d6 c3 c4 u1 r3 u3b u2b fb ovp r12 r1 r5 c2 r4 r22 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pin function description pin no. pin name function pin description 1 css soft ? start select the soft ? start duration 2 fmax frequency clamp a resistor sets the maximum frequency excursion 3 ctimer timer duration sets the timer duration in presence of a fault 4 rt timing resistor connecting a resistor to this pin, sets the minimum oscillator frequency reached for vfb = 1 v 5 bo brown ? out detects low input voltage conditions. when brought above vlatch, it fully latches off the controller. 6 fb feedback injecting current in this pin increases the oscillation frequency up to fmax. 7 dt dead ? time a simple resistor adjusts the dead ? time width 8 fast fault quick fault detection fast shut ? down pin. upon release, a clean startup sequence occurs. can be used for skip cycle purposes. 9 slow fault slow fault detection when asserted, the timer starts to countdown and shuts down the controller at the end of its time duration. 10 gnd analog ground ? 11 mlower low side output drives the lower side mosfet 12 vcc supplies the controller the controller accepts up to 20 v 13 nc not connected increases the creepage distance 14 hb half ? bridge connection connects to the half ? bridge output 15 mupper high side output drives the higher side mosfet 16 vboot bootstrap pin the floating v cc supply for the upper stage
NCP1396A, ncp1396b http://onsemi.com 3 vref rt vdd c idt ? + + dt adj. i = imax for vfb = 5.3 v i = 0 for vfb < vfb_min vref vdd imin vfb vfb_off vref vdd imax vfb = 5 fmax vdd itimer if fault itimer else 0 ? + timer + vref pon reset fault vdd iss ss fb rfb ? + + vfb_fault ? + g = 1 > 0 only v = v(fb) ? vfb_min idt vref vdd + vfb_min dt deadtime adjustment vdd ? + bo + vbo ? + + vlatch 20 s noise filter clk d s q q r s qq r pon reset 50% dc temperature shutdown vcc management pon reset fault timeout fault vref bo reset ff + ? + vref fault fast fault v cc timeout fault ss fault mlower gnd figure 2. internal circuit architecture ibo 20 s noise filter 20 ns noise filter + ? slow fault + vref fault nc v boot mupper hb uvlo level shifter fast fault
NCP1396A, ncp1396b http://onsemi.com 4 maximum ratings rating symbol value unit high v oltage bridge pin, pin 14 vbridge ? 1 to 600 v floating supply voltage, ground referenced vboot ? vbridge 0 to 20 v high side output voltage vdrv_hi vbridge ? 0.3 to vboot+0.3 v low side output voltage vdrv_lo ? 0.3 to v cc + 0.3 v allowable output slew rate dvbridge/dt 50 v/ns power supply voltage, pin 12 vcc 20 v maximum voltage, all pins (except pin 11 and 10) ? ? 0.3 to 10 v thermal resistance ? junction ? to ? air, pdip version r ja 100 c/w thermal resistance ? junction ? to ? air, soic version r ja 130 c/w storage temperature range ? ? 60 to +150 c esd capability, hbm model (all pins except v cc and hv) ? 2 kv esd capability, machine model (all pins except pin 11 ? see note 1) ? 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil ? std ? 883, method 3015 machine model method 200 v esd capability, machine model for pin 11 is 180 v. 2. this device meets latch ? up tests defined by jedec standard jesd78.
NCP1396A, ncp1396b http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 12 v, unless otherwise noted.) characteristic pin symbol min typ max unit supply section turn ? on threshold level, vcc going up ? a version 12 vcc on 12.3 13.3 14.3 v turn ? on threshold level, vcc going up ? b version 12 vcc on 9.5 10.5 11.5 v minimum operating voltage after turn ? on 12 vcc (min) 8.5 9.5 10.5 v startup voltage on the floating section 16 ? 14 vboot on 8 9 10 v cutoff voltage on the floating section 16 ? 14 vboot (min) 7.4 8.4 9.4 v startup current, vcc < vcc on 12 istartup ? ? 300 a vcc level at which the internal logic gets reset 12 vcc reset ? 6.5 ? v internal ic consumption, no output load on pin 15/14 ? 11/10, fsw = 300 khz 12 icc1 ? 4 ? ma internal ic consumption, 1 nf output load on pin 15/14 ? 11/10, fsw = 300 khz 12 icc2 ? 11 ? ma consumption in fault mode (all drivers disabled, v cc > v cc(min) ) 12 icc3 ? 1.2 ? ma voltage control oscillator (vco) characteristic pin symbol min typ max unit minimum switching frequency, rt = 18 k on pin 4, vpin 6 = 0.8 v, dt = 300 ns 4 fsw min 58.2 60 61.8 khz maximum switching frequency, rfmax = 1.3 k on pin 2, vpin 6 > 5.3 v, rt = 18 k , dt = 300 ns 2 fsw max 425 500 575 khz feedback pin swing above which f = 0 6 fbsw ? 5.3 ? v operating duty ? cycle symetry 11 ? 15 dc 48 50 52 % delay before any driver re ? start in fault mode ? tdel ? 20 ? s feedback section characteristic pin symbol min typ max unit internal pull ? down resistor 6 rfb ? 20 ? k voltage on pin 6 below which the fb level has no vco action 6 vfb_min ? 1.2 ? v voltage on pin 6 below which the controller considers a fault 6 vfb_off ? 0.6 ? v drive output characteristic pin symbol min typ max unit output voltage rise ? time @ cl = 1 nf, 10 ? 90% of output signal 15 ? 14/1 1 ? 10 t r ? 40 ? ns output voltage fall ? time @ cl = 1 nf, 10 ? 90% of output signal 15 ? 14/1 1 ? 10 t f ? 20 ? ns source resistance 15 ? 14/1 1 ? 10 r oh ? 13 ? sink resistance 15 ? 14/1 1 ? 10 r ol ? 5.5 ? dead time with r dt = 10 k from pin 7 to gnd 7 t_dead 250 300 340 ns maximum dead ? time with r dt = 82 k from pin 7 to gnd 7 t_dead ? max ? 2 ? s minimum dead ? time, r dt = 3 k from pin 7 to gnd 7 t_dead ? min ? 100 ? ns leakage current on high voltage pins to gnd 14, 15,16 ihv_leak ? ? 5 a 3. the a version does not activate soft ? start (unless the feedback pin voltage is below 0.6 v) when the fast ? fault is released, this is for skip cycle implementation. the b version does activate the soft ? start upon release of the fast ? fault input for any feedback conditions. 4. guaranteed by design
NCP1396A, ncp1396b http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 12 v, unless otherwise noted.) timers characteristic pin symbol min typ max unit timer charge current 3 itimer ? 160 ? a timer duration with a 1 f capacitor and a 1 m resistor 3 t ? timer ? 25 ? ms timer recurrence in permanent fault, same values as above 3 t ? timerr ? 1.4 ? s voltage at which pin 3 stops output pulses 3 vtimeron 3.5 4 4.4 v voltage at which pin 3 re ? starts output pulses 3 vtimeroff 0.9 1 1.1 v soft ? start ending voltage 1 vss ? 2 ? v soft ? start charge current 1 iss 80 105 125 a soft ? start duration with a 100 nf capacitor (note 3) 1 t ? ss ? 1.8 ? ms protection characteristic pin symbol min typ max unit reference voltage for fast input (note 4) 8 ? 9 vreffaultf 1.00 1.05 1.10 v hysteresis for fast input (note 4) 8 ? 9 hystefaultf ? 80 ? mv reference voltage for slow input 8 ? 9 vreffaults 0.95 1.00 1.05 v hysteresis for slow input 8 ? 9 hystefaults ? 60 ? mv propagation delay for fast fault input drive shutdown 8 tpfault ? 55 90 ns brown ? out input bias current 5 ibobias ? 0.02 ? a brown ? out level (note 4) 5 vbo 0.99 1.04 1.09 v hysteresis current, vpin5 > vbo ? a version 5 ibo_a 21.5 26.5 31.5 a hysteresis current, vpin5 > vbo ? b version 5 ibo_b 86 106 126 a latching voltage 5 vlatch 3.6 4 4.4 v temperature shutdown ? tsd 140 ? ? c hysteresis ? tsdhyste ? 30 ? c 3. the a version does not activate soft ? start (unless the feedback pin voltage is below 0.6 v) when the fast ? fault is released, this is for skip cycle implementation. the b version does activate the soft ? start upon release of the fast ? fault input for any feedback conditions. 4. guaranteed by design
NCP1396A, ncp1396b http://onsemi.com 7 typical characteristics ? a version 13 13.05 13.1 13.15 13.2 13.25 13.3 13.35 13.4 13.45 13.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vcc on (v) figure 3. vcc on 59.4 59.5 59.6 59.7 59.8 59.9 60 60.1 60.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) frequency (khz) figure 5. fsw min 15 17 19 21 23 25 27 29 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) rfb (k ) figure 7. pulldown resistor (rfb) 9.34 9.36 9.38 9.4 9.42 9.44 9.46 9.48 9.5 9.52 9.54 9.56 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vccmin (v) figure 4. vcc(min) 493 494 495 496 497 498 499 500 501 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) frequency (khz) figure 6. fsw max 1.02 1.025 1.03 1.035 1.04 1.045 1.05 1.055 1.06 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vreffaultff (v) figure 8. fast fault (vreffaultf)
NCP1396A, ncp1396b http://onsemi.com 8 11 12 13 14 15 16 17 18 19 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) roh ( ) figure 9. source resistance (roh) 99 100 101 102 103 104 105 106 107 108 109 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) dt_min (ns) figure 11. t_dead_min 1.958 1.96 1.962 1.964 1.966 1.968 1.97 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) dt_max (us) figure 13. t_dead_max 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) rol ( ) figure 10. sink resistance (rol) 286 287 288 289 290 291 292 293 294 295 296 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) dt_nom (ns) figure 12. t_dead_nom 3.91 3.915 3.92 3.925 3.93 3.935 3.94 3.945 3.95 3.955 3.96 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vlatch (v) figure 14. latch level (vlatch)
NCP1396A, ncp1396b http://onsemi.com 9 1.02 1.025 1.03 1.035 1.04 1.045 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vbo (v) figure 15. brown-out reference (vbo) 25 25.2 25.4 25.6 25.8 26 26.2 26.4 26.6 26.8 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) ibo (ua) figure 16. brown-out hysteresis current (ibo)
NCP1396A, ncp1396b http://onsemi.com 10 typical characteris tics ? b version 10.3 10.35 10.4 10.45 10.5 10.55 10.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vcc on (v) figure 17. vcc on 59.3 59.4 59.5 59.6 59.7 59.8 59.9 60 60.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) frequency (khz) figure 19. fsw min 15 17 19 21 23 25 27 29 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) rfb (k ) figure 21. pulldown resistor (rfb) 9.34 9.36 9.38 9.4 9.42 9.44 9.46 9.48 9.5 9.52 9.54 9.56 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vccmin (v) figure 18. vcc(min) 495 496 497 498 499 500 501 502 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) frequency (khz) figure 20. fsw max 1.025 1.03 1.035 1.04 1.045 1.05 1.055 1.06 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vreffaultff (v) figure 22. fast fault (vreffaultf)
NCP1396A, ncp1396b http://onsemi.com 11 10 11 12 13 14 15 16 17 18 19 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) roh ( ) figure 23. source resistance (roh) 98 99 100 101 102 103 104 105 106 107 108 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) dt_min (ns) figure 25. t_dead_min 1.958 1.96 1.962 1.964 1.966 1.968 1.97 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) dt_max (us) figure 27. t_dead_max 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) rol ( ) figure 24. sink resistance (rol) 284 285 286 287 288 289 290 291 292 293 294 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) dt_nom (ns) figure 26. t_dead_nom 3.93 3.935 3.94 3.945 3.95 3.955 3.96 3.965 3.97 3.975 3.98 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vlatch (v) figure 28. latch level (vlatch)
NCP1396A, ncp1396b http://onsemi.com 12 1.025 1.03 1.035 1.04 1.045 1.05 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) vbo (v) figure 29. brown-out reference (vbo) 99 100 101 102 103 104 105 106 107 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature ( o c) ibo (ua) figure 30. brown-out hysteresis current (ibo)
NCP1396A, ncp1396b http://onsemi.com 13 application information the ncp1396 a/b includes all necessary features to help building a rugged and safe switch-mode power supply featuring an extremely low standby power. the below bullets detail the benefits brought by implementing the ncp1396 controller: ? wide frequency range : a high-speed voltage control oscillator allows an output frequency excursion from 50 khz up to 500 khz on mlower and mupper outputs. ? adjustable dead-time : thanks to a single resistor wired to ground, the user has the ability to include some dead-time, helping to fight cross-conduction between the upper and the lower transistor. ? adjustable soft - start : every time the controller starts to operate (power on), the switching frequency is pushed to the programmed maximum value and slowly moves down toward the minimum frequency, until the feedback loop closes. the soft-start sequence is activated in the following cases: a) normal startup b) back to operation from an off state: during hiccup faulty mode, brown-out or temperature shutdown (tsd). in the NCP1396A, the soft-start is not activated back to operation from the fast fault input, unless the feedback pin voltage is below 0.6 v. to the opposite, in the b version, the soft-start is always activated back from the fast fault input whatever the feedback level is. ? adjustable minimum and maximum frequency excursion : in resonant applications, it is important to stay away from the resonating peak to keep operating the converter in the right region. thanks to a single external resistor, the design er can program its lowest frequency point, obtained in lack of feedback voltage (during the startup sequence or in short-circuit conditions). internally trimmed capacitors offer a 3% precision on the selection of the minimum switching frequency. the adjustable upper stop being less precise to 15%. ? low startup current : when directly powered from the high-voltage dc rail, the device only requires 300 a to start-up. in case of an auxiliary supply, the b version offers a lower start-up threshold to cope with a 12 v dc rail. ? brown-out detection : to avoid operation from a low input voltage, it is interesting to prevent the controller from switching if the high-voltage rail is not within the right boundaries. also, when teamed with a pfc front-end circuitry, the brown-out detection can ensure a clean start-up sequence with soft-start, ensuring that the pfc is stabilized before energizing the resonant tank. the a version features a 27 a hysteresis current for the lowest consumption and the b version slightly increases this current to 100 a in order to improve the noise immunity. ? adjustable fault timer duration : when a fault is detected on the slow fault input or when the fb path is broken, a timer starts to charge an external capacitor. if the fault is removed, the timer opens the charging path and nothing happens. when the timer reaches its selected durati on (via a capacitor on pin 3), all pulses are stopped. the controller now waits for the discharge via an ex ternal resistor of pin 3 capacitor to issue a new cl ean startup sequence with soft-start. ? cumulative fault events : in the NCP1396A/b, the timer capacitor is not reset when the fault disappears. it actually integrates the information and cumulates the occurrences. a resistor placed in parallel with the capacitor will offer a simple way to adjust the discharge rate and thus the auto-recovery retry rate. ? fast and slow fault detection : in some application, subject to heavy load transients, it is interesting to give a certain time to the fault circuit, before activating the protection. on the other hands, some critical faults cannot accept any delay before a corrective action is taken. for this reason, the NCP1396A/b includes a fast fault and a slow fault input. upon assertion, the fast fault immediately stops all pulses and stays in the position as long as the driving signal is high. when released low (the fault has gone), the controller has several choices: in the a version, pulses are back to a level imposed by the feedback pin without soft-start, but in the b version, pulses are back through a regular soft-start sequence. ? skip cycle possibility : the absence of soft-start on the NCP1396A fast fault input offers an easy way to implement skip cycle when power saving features are necessary. a simple resistive connection from the feedback pin to the fast fault input, and skip can be implemented. ? broken feedback loop detection : upon start-up or any time during operation, if the fb signal is missing, the timer starts to charge a capacitor. if the loop is really broken, the fb level does not grow-up before the timer ends counting. the controller then stops all pulses and waits that the timer pin voltage collapses to 1v typically before a new attempt to re-start, via the soft-start. if the optocoupler is permanently broken, a hiccup takes place. ? finally, two circuit versions, a and b : the a and b versions differ because of the following changes:
NCP1396A, ncp1396b http://onsemi.com 14 1. the startup thresholds are different, the a starts to pulse for vcc = 13.3 v whereas the b pulses for vcc = 10.5 v. the turn off levels are the same however. the a is recommended for consumer products where th e designer can use an external startup resistor, whereas the b is more recommended for industrial / medical applications where a 12 v auxiliary supply directly powers the chip. 2. the a version does not activate the soft-start upon release of the fast fault input. this is to let the designer implement skip cycle. to the opposite, the b version goes back to operation upon the fast fault pin release via a soft-start sequence. voltage-controlled oscillator the vco section features a high-speed circuitry allowing operation from 100 khz up to 1 mhz. however, as a division by two internally creates the two q and qbar outputs, the final effective signal on output mlower and mupper switches between 50 khz and 500 khz. the vco is configured in such a way th at if the feedback pin goes up, the switching frequency also goes up. figure 31 shows the architecture of this oscillator. + - cint s r q q clk d vdd vref rt imin rt sets fmin for vfb = 0 vdd vref dt imin rdt sets the dead-time idt fmax vdd fmax sets the maximum fsw vcc fb rfb 20k 0 to i_fmax max fs w max vfb < vb_off ? start fault timer a b vb_off fbint e r na l figure 31. the simplified vco architecture
NCP1396A, ncp1396b http://onsemi.com 15 the designer needs to program the maximum switching frequency and the minimum switching frequency. in llc configurations, for circuits working above the resonant frequency, a high precision is required on the minimum frequency, hence the 3% specification. this minimum switching frequency is actually reached when no feedback closes the loop. it can happen during the startup sequence, a strong output transient loading or in a short-circuit condition. by installing a resistor from pin 4 to gnd, the minimum frequency is set. using the same philosophy, wiring a resistor from pin 2 to gnd will set the maximum frequency excursion. to improve the circuit protection features, we have purposely created a dead zone, where the feedback loop has no action. this is typically below 1.2 v. figure 32 details the arrangement where the internal voltage (that drives the vco) varies between 0 and 2.3 v. however, to create this swing, the feedback pin (to which the optocoupler emitter connects), will need to swing typically between 1.2 v and 5.3 v. + - r1 11.3 k r2 8.7 k r3 100 k d1 2.3v vre f 0.5 v fb fmax rfmax vcc figure 32. the opamp arrangement limits the vco modulation signal between 0.5 and 2.3v this techniques allows us to detect a fault on the converter in case the fb pin cannot rise above 0.6 v (to actually close the loop) in less than a duration imposed by the programmable timer. please refer to the fault section for detailed operation of this mode. as shown on figure 32, the internal dynamics of the vco control voltage will be constrained between 0.5 v and 2.3 v, whereas the feedback loop will drive pin 6 (fb) between 1.2v and 5.3 v. if we take the default fb pin excursion numbers, 1.2 v = 50 khz, 5.3 v = 500 khz, then the vco maximum slope will be 1 . 4 50 500 k k ? = 109.7khz / v. figure 33 and 34 portray the frequency evolution depending on the feedback pin voltage level in a different frequency clamp combination. figure 33. maximal default excursion, rt = 22 k on pin 4 and rfmax = 1.3 k on pin 2. figure 34. here a different minimum frequency was programmed as well as a maximum frequency excursion. please note that the previous small-signal vco slope has now been reduced to 300k / 4.1 = 73 khz / v on mupper and mlower outputs. this of fers a mean to magnify the feedback excursion on systems where the load range does not generate a wide switching frequency excursion. thanks to this option, we will see how it becomes possible to observe the feedba ck level and implement skip cycle at light loads. it is important to note that the frequency evolution does not have a real linear relationship with the feedback voltage. this is due to the deadtime presence which stays constant as the switching period changes.
NCP1396A, ncp1396b http://onsemi.com 16 the selection of the three setting resistors (fmax, fmin deadtime) requires the usage of the selection charts displayed below: 50 150 250 350 450 550 650 1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5 17.5 rfmax (k ) fmax (khz) fmin = 50 fmin = 200 khz vcc = 12 v fb = 6.5 v dt = 300 ns figure 35. maximum switching frequency resistor selection depending on the adopted minimum switching frequency 20 70 120 170 220 270 320 370 420 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 rfmin (k ) fmin (khz) vcc = 12 v fb = 1 v dt = 300 ns figure 36. minimum switching frequency resistor selection 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 3.5 8.5 13.5 18.5 23.5 28.5 33.5 38.5 43.5 48.5 53.5 58.5 63.5 68.5 73.5 78.5 83.5 rdt (k ) dt (ns) vcc = 12v figure 37. dead-time resistor selection oring capability if for any particular reason, there is a need for a frequency variation linked to an event appearance (instead of abruptly stopping pulses), then the fb pin lends itself very well to the addition of other sweeping loops. several diodes can easily be used perform the job in case of reaction to a fault event or to regulate on the output current (cc operation). figure 38 shows how to do it. 20k vcc vco fb in1 in2 figure 38. thanks to the fb configuration, loop oring is easy to implement dead-time control dead-time control is an absolute necessity when the half-bridge configuratio n comes to play. the dead- time technique consists in inserting a period during which both high and low side switches are off. of course, the dead-time amount differs depending on the switching frequency, hence the ability to adjust it on this controller. the option ranges between 100 ns and 2 us. the dead- time is actually made by controlling the oscillator discharge current. figure 39 portrays a simplified vco circuit based on figure 31.
NCP1396A, ncp1396b http://onsemi.com 17 + - s r q q clk d icharge : fsw min + fsw max ct 3v - 1v vdd idis vref rdt a b dt figure 39. dead-time generation during the discharge time, th e clock comparator is high and un-validates the and gates: both outputs are low. when the comparator goes b ack to the low level, during the timing capacitor ct rechar ge time, a and b outputs are validated. by connecting a resistor rdt to ground, it creates a current whose image serves to discharge the ct capacitor: we control the de ad-time. the typical range evolves between 100 ns (rdt = 3.5 k ) and 2 us (rdt = 83.5 k ). figure 42 shows the typical waveforms. soft-start sequence in resonant controllers, a soft-start is needed to avoid suddenly applying the full current into the resonating circuit. in this controller, a soft-start capacitor connects to pin 1 and offers a smooth frequency variation upon start-up: when the circuit starts to pulse, the vco is pushed to the maximum switching frequency imposed by pin 2. then, it linearly decreases its frequency toward the minimum frequency selected by a resistor on pin 4. of course, practically, the feedback loop is suppose to take over the vco lead as soon as the output voltage has reached the target. if not, then the minimum switching frequency is reached and a fault is detected on the feedback pin (typically below 600mv). figure 40 depicts a typical frequency evolution with soft-start. -20.0 -10.0 0 10.0 20.0 ires1 in amperes plot1 1 200u 600u 1.00m 1.40m 1.80m time in seconds 169 171 173 175 177 vout in volts plot2 2 figure 40. soft-start behavior figure 41. a typical star t-up sequence on a llc converter ires vout ss action target is reached
NCP1396A, ncp1396b http://onsemi.com 18 please note that the soft-start will be activated in the following conditions: ? a startup sequence ? during auto ? recovery burst mode ? a brown ? out recovery ? a temperature shutdown recovery the fast fault input undergoe s a special treatment. since we want to implement skip cycle through the fast fault input on the NCP1396A, we cannot activate the soft ? start every time the feedback pin stops the operations in low power mode. therefore, when the fast fault pin is released, no soft ? start occurs to offer the best skip cycle behavior. however, it is very possible to combine skip cycle and true fast fault input, e.g. via oring diodes driving pin 6. in that case, if a signal maintains the fast fault input high long enough to bring the feedback level down (that is to say below 0.6 v) since the output voltage starts to fall down, then the soft ? start is activated after the release of the pin. in the b version tailored to operate from an auxiliary 12 v power supply, the soft ? start is always activated upon the fast fault input release, whatever the feedback condition is. 0 1.00 2.00 3.00 4.00 vct in volts plot1 0 4.00 8.00 12.0 16.0 clock in volts plot2 56.2u 65.9u 75.7u 85.4u 95.1u ti i d -8.00 -4.00 0 4.00 8.00 difference in volts plot3 figure 42. typical oscillator waveforms brown-out protection the brown-out circuitry (bo) offers a way to protect the resonant converter from low dc input voltages. below a given level, the controller blocks the output pulses, above it, it authorizes them. the internal circuitry, depicted by figure 43, offers a way to observe the high-voltage (hv) rail. a resistive divider made of rupper and rlower, brings a portion of the hv rail on pin 5. below the turn-on level, the 27a current source ibo is off. therefore, the turn-on level solely depends on the division ratio brought by the resistive divider. ct voltage clock pulses dt dt dt a ? b
NCP1396A, ncp1396b http://onsemi.com 19 + - rupper rlower vbulk vdd bo ibo bo vbo on/off 20.0u 60.0u 100u 140u 180u 0 4.00 8.00 12.0 16.0 vcmp in volts 50.0 150 250 350 450 vin in volts plot1 1 2 250 volts 351 volts figure 43. the internal brown-out configuration with fi gure 44. simulation results for 350 / 250 on / off levels an offset current source to the contrary, when the internal bo signal is high (mlower and mupper pulse), the ibo source is activated and creates a hysteresis. as a result, it becomes possible to select the turn-on and turn-o ff levels via a few lines of algebra: ibo is off () 1 rlower v vbulk r lower rupper += + eq. 1 ibo is on () 2 r lower rlower rupper v vbulk ibo r lower rupper rlower rupper ?? += + ?? ++ ?? eq. 2 we can now extract rlower from equation 1 and plug it into equation 2, then solve for rupper: 1 vbulk vbo rupper rlower vbo ? = () 12 1 vbulk vbulk rlower vbo i bo vbulk vbo ? = ? if we decide to turn-on our converter for vbulk1 equals 350v and turn it off for vbulk2 equals 250v, then we obtain: rupper = 1m rlower = 2.86k the bridge power dissipation is 4002 / 1.00286m = 160mw when front-end pfc stage delivers 400v. figure 44 simulation result confirms our calculations. latch-off protection there are some situati ons where the converter shall be fully turned-off and stay latched. this can happen in presence of an over-voltage (the feedback loop is drifting) or when an over te mperature is detected. thanks to the addition of a comparator on the bo pin, a simple external circuit can lift up this pin above vlatch (4 v typical) and permanently disabl e pulses. the vcc needs to be cycled down below 6.5 v typically to reset the controller. bo vin
NCP1396A, ncp1396b http://onsemi.com 20 + - + - vdd bo rupper rlower ibo vbulk to permanent latch vlatch vbo q1 vcc vout ntc bo 20us rc figure 45. adding a comparator on the bo pin offers a way to latch-off the controller on figure 45, q1 is blocked and does not bother the bo measurement as long as the ntc and the optocoupler are not activated. as soon as the secondary optocoupler senses an ovp condition, or the ntc reacts to a high ambient temperature, q1 base is brought to ground and the bo pin goes up, permanently latching off the controller. protection circuitry this resonant controller differs from competitors thanks to its protection features. the device can react to various inputs like: - fast events input : like an over-current condition, a need to shut down (sleep mode) or a way to force a controlled burst mode (skip cycle at low output power): as soon as the input level exceeds 1v typi cal, pulses are immediately stopped. when the input is released, the controller performs a clean startup sequ ence including a soft-start period. -slow events input : this input serves as a delayed shutdown, where an event lik e a transient overload does not immediately stopped pulses but start a timer. if the event duration lasts longer than what the timer imposes, then all pulses are disabled. the voltage on the timer capacitor (pin 3) starts to de crease until it reaches 1v. the decrease rate is actually depending on the resistor the user will put in parallel with the capacitor, giving another flexibility during design. figure 46 depicts the architecture of the fault circuitry.
NCP1396A, ncp1396b http://onsemi.com 21 + - ctimer vreffault itimer + - vdd a b driving logic vcc vreffault av erage input current uvlo slow fault fast fault a b reset on/off ctimer + - vtimeron vtimeroff 1 = ok 0 = fault 1 = ok 0 = fault ss reset 1 = fault 0 = ok rtimer fb fb skip to primary current sensing circuitry figure 46. this circuit combines a slow and fast input for improved protection features. slow input on this circuit, the slow input goes to a comparator. when this input exceeds 1v typical, the current source itimer turn s on, charging the external capacitor ctimer. if the fault duration is long enough, when ctimer voltage reaches the vtimeron level (4v typical), then all pulses are stopped. if the fault input signal is still present, then the controller permanently stays off and the voltage on the timer capacitor does not move (itimer is on and the voltage is clamped to 5v). if the fault input signal is removed (because pulses are off for instance), itimer turns off and the capacitor slowly discharges to ground via a resistor installed in parallel with it. as a result, the designer can easily determine the time during which the power supply stays locked by playing on rtimer. now, when the timer capacitor voltage reaches 1v typical (vtimeroff) , the comparator instructs the internal logic to issues pu lses as on a clean soft-start sequence (soft-start is activat ed). please note that the discharge resistor can not be lower than 4v / itimer otherwise the voltage on ctim er will not reach the turn- off voltage of 4v. in both cases, when the fault is validated, both outputs mlower and mupper are in ternally pulled down to ground. on figure 46 example, a voltage proportional to primary current, once averaged, gives an image of the input power in case vin is kept constant via a pfc circuit. if the output loading increases above a certain level, the voltage on this pin will pass the 1v threshold and start the timer. if the overload stays there, after a few tens of milli- seconds, switching pulses will disappear and a protective auto-recovery cycle will take place. adjusting the resistor r in parallel with the timer capacitor will give the flexibility to adjust the fault burst mode.
NCP1396A, ncp1396b http://onsemi.com 22 2 vcc 3 fb fast fault figure 47. a resistor can easily program th e capacitor discharge time figu re 48. skip cycle can be implemented via two resistors on the fb pin to the fast fault input. fast input the fast input is not affected by a delayed action. as soon as its voltage exceeds 1v typical, all pulses are off and maintained off as long as the fault is present. when the pin is released, pulses come back and the soft- start is activated. thanks to the low activation level of 1v, this pin can observe the feedback pin via a resistive divided and thus implement skip cycle operation. the resonant converter can be designed to lose regulation in light load conditions, forcing the fb level to increase. when it reaches the programmed level, it triggers the fast fault input and stops pulses. then vout slowly drops, the loop reacts by decreasing the feedback level which, in turn, unlocks the pulses, vout goes up again and so on: we are in skip cycle mode. startup behaviour when the vcc voltage grows-up, the internal current consumption is kept to istrup, allowing to crank- up the converter via a resistor connected to the bulk capacitor. when vcc reaches the vccon level, output mlower goes high first and then output mupper. this sequence will always be the same whatever triggers the pulse delivery: fault, off to on etc? pulsing the output mlower high first gives an immediate charge of the bootstrap capacitor. then, the rest of pulses follow, delivered at the highest switching value, set by the resistor on pin 2. the soft-start capacitor ensures a smooth frequency decrease to either the programmed minimum value (in case of fault) or to a value corres ponding to the operating point if the feedback loop closes first. figure 49 shows typical signals evolution at power on.
NCP1396A, ncp1396b http://onsemi.com 23 figure 49. at power on, output a is first activated and th e frequency slowly decreases via the soft-start capacitor figure 49 depicts an auto-r ecovery situation, where the timer has triggered the end of output pulses. in that case, the vcc level was given by an auxiliary power supply, hence its stability during the hiccup. a similar situation can arise if the user selects a more traditional startup method, with an auxiliary winding. in that case, the vcc(min) comparator stops th e output pulses whenever it is activated, that is to say, when vcc falls below 10v typical. at this time, the vcc pin still receives its bias current from the startup resi stor and heads toward vcc on via the vcc capacitor. when the voltage reaches vcc on , a standard sequence takes pl ace, involving a soft-start. figure 50 portrays this behavior.
NCP1396A, ncp1396b http://onsemi.com 24 figure 50. when the vcc is too low, all pulses are stopped until vcc goes back to the startup voltage as described in the data-sheet, two startup levels vcc on are available, via two circ uit versions. the ncp1396 features sufficient hysteresis (3v typically) to allow a classical startup method with a resistor connected to the bulk capacitor. then, at the end of the startup sequence, an auxiliary winding is supposed to take over the controller supply voltage. to the opposite, for applications where the resonant controller is powered from a standby power supply, the startup level is 10v typically and allows for the direct a connection from a 12v source. thanks to this ncp1396b, simple on/off operation is therefore feasible. the high-voltage driver the driver features a traditional bootstrap circuitry, requiring an external high-voltage diode for the capacitor refueling path. figure 51 shows the internal architecture of the hi gh-voltage section.
NCP1396A, ncp1396b http://onsemi.com 25 vboot mupper hb vcc mlower gnd s r q q uvlo level shifter pulse trigger a b fault cboot dboot delay hv aux vcc figure 51. the internal high-voltage section of the ncp1396 the device incorporates an upper uvlo circuitry that makes sure enough vgs is available for the upper side mosfet. the b and a outputs are delivered by the internal logic, as figure 46 testifies. a delay is inserted in the lower rail to ensure good matching between these propagating signals. as stated in the maximum rating section, the floating portion can go up to 600vdc and makes the ic perfectly suitable for offline applica tions featuring a 400v pfc front-end stage.
NCP1396A, ncp1396b http://onsemi.com 25 package dimensions pdip ? 16 p suffix case 648 ? 08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 so ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
NCP1396A, ncp1396b http://onsemi.com 26 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1396/d note: the product described herein (NCP1396A/b), is covered by u.s. patent: 6,097, 075; 7176723; 6,362, 067. there may be some other patent pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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